Core Applications
Covers post-CMP roughness, film thickness uniformity, etch-depth analysis, and high-precision 3D critical dimensions for MEMS.
Semiconductor & Electronics
Photolithography
Photoresist: 100 nm - 10 um, Controls lithography pattern accuracy and impacts chip yield
Insulation / Passivation
Dielectric films (SiO₂, Si₃N₄): 10 nm - 1 um, Gate oxide layer, interlayer dielectric; determines electrical performance of devices
Flexible Circuit Protection
Polyimide (PI) / UV coating: 5 um - 50 um, FPC insulating protective layer; thickness affects flexibility and reliability
Key Technology Selection
Non-contact white-light interferometry enables nanoscale 3D topography without wafer damage—meeting strict semiconductor process needs.
Automated Measurement workflow
Multi-point auto-scan of the wafer; real-time capture with auto Sa/Sq roughness and film thickness uniformity (TTV) metrics.
Process & Yield Gains
Real-time control keeps Ra < 0.1 nm, feeds back process tweaks, suppresses defects, and significantly raises chip yield.
Application Case
Wafer surface inspection flow: silicon wafer, 3D topography scan, and key profile metrics—showing micro-morphology analysis.
Frequently Asked Questions
Which thin films are measured in semiconductor and electronics manufacturing?
TDM metrology covers photoresist (typically 100 nm–10 µm) that controls lithography pattern accuracy and yield; dielectric films such as SiO₂ and Si₃N₄ (10 nm–1 µm) used as gate oxide and interlayer insulation; and polyimide or UV coatings (5–50 µm) that protect flexible circuits. Post-CMP roughness, thickness uniformity, etch depth and MEMS 3D critical dimensions are also in scope.
Why does photoresist thickness matter for photolithography?
Photoresist thickness in the 100 nm–10 µm range controls pattern transfer accuracy. If the film is too thick or too thin, CD (critical dimension) drifts and chip yield drops. Non-destructive optical measurement verifies the resist before exposure without damaging the wafer.
How can wafer films be measured without contact or damage?
Non-contact white-light interferometry maps nanoscale 3D topography without touching the wafer, which meets semiconductor process rules that forbid mechanical probes on product wafers. The same non-contact approach is used for dielectric thickness and post-CMP roughness.
How does automated wafer scanning improve process yield?
Multi-point auto-scan captures Sa/Sq roughness and film-thickness uniformity (TTV) in real time. Closed-loop feedback is used to keep Ra below 0.1 nm, suppress defects and raise chip yield compared with offline sampling alone.
Talk to us about your film stack
Photoresist, SiO₂ and Si₃N₄ gate oxide, polyimide and UV coatings, post-CMP roughness, etch depth and MEMS critical dimensions are all within our published measurement range of 4 nm–450 µm.
Send us your layer stack, substrate and target thickness. We'll reply with the instrument and measurement range that fits, and run a free sample test on your own wafer before you commit.